Design of Low Power Transposition RAM Using Optimized Memory Primitives
نویسنده
چکیده
In this paper, a low power single edge triggered D flip-flop is presented by using True Single Phase Clocked technique (TSPC). The proposed design overcomes the problem of race condition at the output caused by clock pulses. This technique uses single phase clock pulse and it has less number of transistors. All the circuits are designed and simulated using Cadence® Virtuoso® Design Environment provided by Cadence Design Systems. Generic Process Design Kit (GPDK) 45nm technology file is used to get the transistor models. It is evident from the performance comparisons at 100% switching activity; the proposed flip-flop can save up to 91% power, 77.2% delay and 98.2% power-delayproduct (PDP) as compared to the conventional master-slave edge triggered flip-flop.
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